1. Field of the Invention
The present invention relates to a process for fabricating a capacitor, and more particularly the invention relates to a process for fabricating a capacitor used in a memory cell of a DRAM.
2. Description of the Prior Art
The size of a capacitor in a memory cell is very important to a DRAM (dynamic random access memory), which directly influences the time interval required for the information renewal of the DRAM and which indirectly influences the reading speed on Information stored in the DRAM as well. Therefore, many efforts have been made to increase the capacitance value of a capacitor.
Capacitors can be classified structurally into two kinds: one is the trench capacitor and the other is the stacked capacitor. In order to increase the capacitance value of a trench capacitor, the depth of the trench capacitor should be enlarged, which will adversely result in too large a leakage current and a decreased reliability. Therefore, trench capacitors are not suitable for use when there is a need to increase the capacitance. Stacked capacitors on the other hand are more suitable or this purpose.
Enlarging coupling areas of the top and bottom electrodes of a capacitor is a way to increase the capacitance value. However, as the feature size of a semiconductor device is decreased, a more complicated process will typically be required for such a structural change, resulting in an escalation of production cost. Therefore, researchers have been increasingly focusing their attention on how to increase the capacitance value of a capacitor by carefully selecting different capacitor materials.
Conventionally, the top and bottom electrodes of a capacitor are made of polysilicon, and the dielectric layer situated between the electrodes is typically made of silicon oxide or silicon nitride. The dielectric constant of silicon oxide or silicon nitride is typically not high, or only seven at the most, and since the thickness of the dielectric layer can not be made too thin, the increase in the capacitance value is thus limited. Or the other hand, depletion region is easily formed in the top and bottom electrodes of a polysilicon capacitor, which causes the capacitance value to be decreased.
Since (Ba,Sr)TiO3 (BST) has a dielectric constant as high as 500, using the BST material as the dielectric layer to increase the capacitance value of a capacitor has become a very popular topic recently. In addition, in order to solve the problem caused by depletion regions formed in the top and bottom polysilicon electrodes and leakage current resulted from the interface between the dielectric layer and the polysilicon, the material of choice for the top and bottom electrodes has been gradually replaced by a metal. Such capacitors having the top and bottom electrodes made of metal material are called metal-insulator-metal (MIM) capacitors. Furthermore, since platinum has the advantages of low leakage current and high thermal stability, it is very suitable for use as a metal electrode.
Generally, the bottom electrode of an MIM capacitor is fabricated by first forming a metal layer on a semiconductor substrate through a physical vapor deposition process or a chemical vapor deposition process, then the contour of the metal layer is further defined by means of a photo-etching process, in order to carve out a specific shape for the bottom electrode. Nonetheless, due to the unique physical characteristics of the platinum metal, it is very difficult to form a bottom electrode with platinum hat is capable of achieving an accurate critical dimension (CD) defined by a photo-eching process. Therefore, a need lo develop a new process for forming a platinum bottom electrode with accurate critical dimensions arises.
Accordingly, an object of the present invention is to solve the above-mentioned problems and to provide an improved process that can avoid the problems occurred during an etching process for platinum. as the difficulty in controlling the critical dimension needs to be counteracted.
To achieve the above object, the present invention provides a process for fabricating a capacitor. First, a first dielectric layer is formed on a substrate. Then, a portion of the first dielectric layer is removed to form a contact hole. A conductive plug is formed within the contact hole. A seed layer is formed on the conductive plug. A sacrifice layer is formed on both the seed layer and the first dielectric layer. A predetermined region of the sacrifice layer is removed to form a recess so as to expose he seed layer. Then, a bottom electrode layer is formed by electroplating within the recess. The sacrifice layer is removed afterwards. Finally, a second dielectric layer and a top electrode layer are formed on the bottom electrode Maker In sequence, thus a capacitor is fabricated.
The seed layer is preferably made of ruthenium (Ru). The bottom electrode layer and the top electrode layer are preferably made of platinum (Pt). And the second dielectric layer is preferably made of (Ba,Sr.)TLO3 (BST)
The advantage presented by the present invention is that the etching step to form a pattern of the bottom electrode layer can be completely avoided, so the difficulty in platinum etching and the problem with controlling the respective critical dimensions can be a alleviated.